1. Field of the Invention
The present invention relates to an improvement in a digital-to-analog converter.
2. Description of the Prior Art
FIG. 1 is a connection diagram showing an exemplary construction of a conventional digital-to-analog converter. Referring to FIG. 1, numeral 1 indicates three input terminals for receiving bits which are represented by D.sub.2, D.sub.1 and D.sub.0 respectively. In the example as shown in FIG. 1, the input digital signal is binary codes of the bit number n=3, and hence outputted is an analog signal of eight stages (generally 2.sup.n stages). Numeral 2 indicates a decoder for decoding the input bits, numeral 301 indicates an output terminal for extracting output currents and numeral 302 indicates an output terminal for extracting currents complementary to the currents outputted from the output terminal 301. Numeral 303 indicates a first bus which is connected to the output terminal 301. Numeral 304 indicates a second bus which is connected to the output terminal 302. Numerals 401 to 407 indicate constant current sources which are biased by bias voltage V.sub.B to generate equal unit currents; numerals 501 to 507 indicate switches provided in correspondence to the constant current sources 401 to 407, respectively; numerals 601 to 607 indicate control lines which receive control signals outputted from the decoder 2 to control switching of the corresponding switches 501 to 507; numeral 7 indicates a grounded point; numeral 70 indicates a grounding conductor, such as a grounding lead wire, numerals 701 to 707 indicate respective connection nodes between the constant current sources 401 to 407 and the grounding lead wire 70; and numeral 8 indicates a voltage input terminal for supplying the bias voltage V.sub.B to the constant current sources 401 to 407.
Description is now made on the operation of the digital-to-analog converter as shown in FIG. 1. Assuming that symbol I.sub.0 represents the unit current flowing in the respective one of the constant current sources 401 to 407, the grounded point 7 receives the current of 7I.sub.0. On the other hand, the current flowing to the output terminal 301 is changed by switching states of the switches 501 to 507 in eight stages of 0, I.sub.0, 2I.sub.0, 3I.sub.0, 4I.sub.0, 5I.sub.0, 6I.sub.0 and 7I.sub.0, which represent the amount of the analog signal outputted from the digital-to-analog converter. In case where the inputted signal D.sub.2 D.sub.1 D.sub.0 is in the bit value of "011"representing the numerical value "3" in decimal, arbitrary three of the switches 501 to 507 are leftwardly turned while the remaining switches are rightwardly turned, so that current of 3I.sub.0 flow to the output terminal 301. In the conventional device as shown in FIG. 1, three switches 501, 502 and 503 are leftwardly turned sequentially from the left-hand direction so that the output terminal 303 outputs the current of 3I.sub.0 and the output terminal 302 outputs current of 4I.sub.0 (=7I.sub.0 -3I.sub.0).
In the conventional digital-to-analog converter of the aforementioned construction, a voltage drop is caused by the grounding lead wire 70 since the resistance value thereof is not zero, that is, the grounding lead wire 70 has a prescribed length and it has inner-resistance along the length, so that the bias voltage actually applied to the respective constant current sources 401 to 407 is at the maximum level in the constant current source 401 which is closest to the grounded point 7 and at the minimum level in the constant current source 407 farthest from the grounded point 7.
FIG. 2 is a graph showing the amounts of the currents actually flowing in the respective constant current sources 401 to 407, and assuming that I.sub.0 represents the mean value thereof, the amounts of the current actually flowing in the respective constant current sources 401 to 407 are different from the mean value I.sub.0 by the voltage drops caused by the grounding lead wire 70. Therefore, when, for example, only the switches 501, 502 and 503 are leftwardly turned as shown in FIG. 1 so that the currents flow from the output terminal 301 to the constant current sources 401, 402 and 403, the sum total thereof is greater than 3I.sub.0. In general, this means that the digital-to-analog converter is degraded in linearity.